Initiate PCB_V4; Add submodule for SK6812MINI-E

524d4423 · Valérianne · acae9a2d · 524d4423 · c7ae3b44 · 524d4423
Verified Commit 524d4423 authored Jul 27, 2021 by Valérianne 💬
--- a/.gitmodules
+++ b/.gitmodules
@@ -10,3 +10,6 @@
 [submodule "KiCAD-Keyboard-Tutorial"]
 	path = KiCAD-Keyboard-Tutorial
 	url = https://github.com/BathroomEpiphanies/KiCAD-Keyboard-Tutorial
+[submodule "Keebio-Parts.pretty"]
+	path = Keebio-Parts.pretty
+	url = https://github.com/keebio/Keebio-Parts.pretty
--- a/Keebio-Parts.pretty @ c7ae3b44
+++ b/Keebio-Parts.pretty @ c7ae3b44
+Subproject commit c7ae3b44674679f4d767767c002fed1eacd414a1
--- a/pcb_v4/bom.ini
+++ b/pcb_v4/bom.ini
+[BOM_OPTIONS]
+; General BoM options here
+; If 'ignore_dnf' option is set to 1, rows that are not to be fitted on the PCB will not be written to the BoM file
+ignore_dnf = 1
+; If 'number_rows' option is set to 1, each row in the BoM will be prepended with an incrementing row number
+number_rows = 1
+; If 'group_connectors' option is set to 1, connectors with the same footprints will be grouped together, independent of the name of the connector
+group_connectors = 1
+; If 'test_regex' option is set to 1, each component group will be tested against a number of regular-expressions (specified, per column, below). If any matches are found, the row is ignored in the output file
+test_regex = 1
+; If 'merge_blank_fields' option is set to 1, component groups with blank fields will be merged into the most compatible group, where possible
+merge_blank_fields = 1
+; If '{opt}' option is set to 1, the schematic version number will be appended to the filename.
+include_version_number = 1
+; Field name used to determine if a particular part is to be fitted
+fit_field = Config
+
+[IGNORE_COLUMNS]
+; Any column heading that appears here will be excluded from the Generated BoM
+; Titles are case-insensitive
+Part Lib
+Footprint Lib
+
+[GROUP_FIELDS]
+; List of fields used for sorting individual components into groups
+; Components which match (comparing *all* fields) will be grouped together
+; Field names are case-insensitive
+Part
+Part Lib
+;Value
+Footprint
+Footprint Lib
+
+[COMPONENT_ALIASES]
+; A series of values which are considered to be equivalent for the part name
+; Each line represents a tab-separated list of equivalent component name values
+; e.g. 'c c_small cap' will ensure the equivalent capacitor symbols can be grouped together
+; Aliases are case-insensitive
+c	c_small	cap	capacitor
+r	r_small	res	resistor
+sw	switch
+l	l_small	inductor
+zener	zenersmall
+d	diode	d_small
+
+[REGEX_INCLUDE]
+; A series of regular expressions used to include parts in the BoM
+; If there are any regex defined here, only components that match against ANY of them will be included in the BOM
+; Column names are case-insensitive
+; Format is: "ColumName	Regex" (tab-separated)
+
+[REGEX_EXCLUDE]
+; A series of regular expressions used to exclude parts from the BoM
+; If a component matches ANY of these, it will be excluded from the BoM
+; Column names are case-insensitive
+; Format is: "ColumName	Regex" (tab-separated)
+References	^TP[0-9]*
+References	^FID
+Part	mount.*hole
+Part	solder.*bridge
+Part	test.*point
+Footprint	test.*point
+Footprint	mount.*hole
+Footprint	fiducial
+
--- a/pcb_v4/dashie-keys-rescue.dcm
+++ b/pcb_v4/dashie-keys-rescue.dcm
+EESchema-DOCLIB  Version 2.0
+#
+#End Doc Library
--- a/pcb_v4/dashie-keys-rescue.lib
+++ b/pcb_v4/dashie-keys-rescue.lib
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Conn_01x01-Connector_Generic-dashie-keys-rescue
+#
+DEF Conn_01x01-Connector_Generic-dashie-keys-rescue J 0 40 Y N 1 F N
+F0 "J" 0 100 50 H V C CNN
+F1 "Conn_01x01-Connector_Generic-dashie-keys-rescue" 0 -100 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*
+$ENDFPLIST
+DRAW
+S -50 5 0 -5 1 1 6 N
+S -50 50 50 -50 1 1 10 f
+X Pin_1 1 -200 0 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Conn_01x02-Connector_Generic-dashie-keys-rescue
+#
+DEF Conn_01x02-Connector_Generic-dashie-keys-rescue J 0 40 Y N 1 F N
+F0 "J" 0 100 50 H V C CNN
+F1 "Conn_01x02-Connector_Generic-dashie-keys-rescue" 0 -200 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 50 50 -150 1 1 10 f
+X Pin_1 1 -200 0 150 R 50 50 1 1 P
+X Pin_2 2 -200 -100 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Conn_01x04-Connector_Generic-dashie-keys-rescue
+#
+DEF Conn_01x04-Connector_Generic-dashie-keys-rescue J 0 40 Y N 1 F N
+F0 "J" 0 200 50 H V C CNN
+F1 "Conn_01x04-Connector_Generic-dashie-keys-rescue" 0 -300 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+S -50 -195 0 -205 1 1 6 N
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 150 50 -250 1 1 10 f
+X Pin_1 1 -200 100 150 R 50 50 1 1 P
+X Pin_2 2 -200 0 150 R 50 50 1 1 P
+X Pin_3 3 -200 -100 150 R 50 50 1 1 P
+X Pin_4 4 -200 -200 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Mounting_Hole-Mechanical
+#
+DEF Mounting_Hole-Mechanical MK 0 40 Y Y 1 F N
+F0 "MK" 0 200 50 H V C CNN
+F1 "Mounting_Hole-Mechanical" 0 125 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Mounting?Hole*
+ Hole*
+$ENDFPLIST
+DRAW
+C 0 0 50 0 1 50 N
+ENDDRAW
+ENDDEF
+#
+#End Library
--- a/pcb_v4/dashie-keys.dsn
+++ b/pcb_v4/dashie-keys.dsn
--- a/pcb_v4/dashie-keys.kicad_pcb
+++ b/pcb_v4/dashie-keys.kicad_pcb
--- a/pcb_v4/dashie-keys.net
+++ b/pcb_v4/dashie-keys.net
--- a/pcb_v4/dashie-keys.pro
+++ b/pcb_v4/dashie-keys.pro
+update=mar. 22 sept. 2020 14:25:27
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=dashie-keys.net
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.2
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.25
+TrackWidth2=0.5
+TrackWidth3=0.8
+ViaDiameter1=0.6
+ViaDrill1=0.4
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.15
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.15
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0.2
+SolderMaskMinWidth=0
+SolderPasteClearance=0
+SolderPasteRatio=-0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=In1.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In2.Cu]
+Name=In2.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.25
+ViaDiameter=0.6
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/1]
+Name=GND
+Clearance=0.2
+TrackWidth=0.5
+ViaDiameter=0.6
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/2]
+Name=VCC
+Clearance=0.2
+TrackWidth=0.5
+ViaDiameter=0.6
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
--- a/pcb_v4/dashie-keys.rules
+++ b/pcb_v4/dashie-keys.rules
+
+(rules PCB dashie-keys
+  (snap_angle 
+    fortyfive_degree
+  )
+  (autoroute_settings
+    (fanout off)
+    (eu.mihosoft.freerouting.autoroute on)
+    (postroute on)
+    (vias on)
+    (via_costs 50)
+    (plane_via_costs 5)
+    (start_ripup_costs 100)
+    (start_pass_no 36029)
+    (layer_rule F.Cu
+      (active on)
+      (preferred_direction horizontal)
+      (preferred_direction_trace_costs 1.0)
+      (against_preferred_direction_trace_costs 2.7)
+    )
+    (layer_rule B.Cu
+      (active on)
+      (preferred_direction vertical)
+      (preferred_direction_trace_costs 1.0)
+      (against_preferred_direction_trace_costs 1.6)
+    )
+  )
+  (rule
+    (width 250.0)
+    (clear 200.2)
+    (clear 125.0 (type smd_to_turn_gap))
+    (clear 50.0 (type smd_smd))
+  )
+  (padstack "Via[0-1]_600:400_um"
+    (shape
+      (circle F.Cu 600.0 0.0 0.0)
+    )
+    (shape
+      (circle B.Cu 600.0 0.0 0.0)
+    )
+    (attach off)
+  )
+  (via 
+    "Via[0-1]_600:400_um" "Via[0-1]_600:400_um" default
+  )
+  (via 
+    "Via[0-1]_600:400_um-kicad_default" "Via[0-1]_600:400_um" "kicad_default"
+  )
+  (via 
+    "Via[0-1]_600:400_um-GND" "Via[0-1]_600:400_um" GND
+  )
+  (via 
+    "Via[0-1]_600:400_um-VCC" "Via[0-1]_600:400_um" VCC
+  )
+  (via_rule
+    default "Via[0-1]_600:400_um"
+  )
+  (via_rule
+    "kicad_default" "Via[0-1]_600:400_um-kicad_default"
+  )
+  (via_rule
+    GND "Via[0-1]_600:400_um-GND"
+  )
+  (via_rule
+    VCC "Via[0-1]_600:400_um-VCC"
+  )
+  (class default
+    (clearance_class default)
+    (via_rule default)
+    (rule
+      (width 250.0)
+    )
+    (circuit 
+      (use_layer F.Cu B.Cu)
+    )
+  )
+  (class "kicad_default"
+    ROW1 "Net-(D1-Pad2)" "Net-(D2-Pad2)" "Net-(D3-Pad2)" "Net-(D4-Pad2)" "Net-(D5-Pad2)" "Net-(D6-Pad2)" "Net-(D7-Pad2)"
+    "Net-(D8-Pad2)" "Net-(D9-Pad2)" "Net-(D10-Pad2)" "Net-(D11-Pad2)" "Net-(D12-Pad2)" "Net-(D13-Pad2)" "Net-(D14-Pad2)" ROW2
+    "Net-(D15-Pad2)" "Net-(D16-Pad2)" "Net-(D17-Pad2)" "Net-(D18-Pad2)" "Net-(D19-Pad2)" "Net-(D20-Pad2)" "Net-(D21-Pad2)" "Net-(D22-Pad2)"
+    "Net-(D23-Pad2)" "Net-(D24-Pad2)" "Net-(D25-Pad2)" "Net-(D26-Pad2)" "Net-(D27-Pad2)" "Net-(D28-Pad2)" "Net-(D29-Pad2)" ROW3
+    "Net-(D30-Pad2)" "Net-(D31-Pad2)" "Net-(D32-Pad2)" "Net-(D33-Pad2)" "Net-(D34-Pad2)" "Net-(D35-Pad2)" "Net-(D36-Pad2)" "Net-(D37-Pad2)"
+    "Net-(D38-Pad2)" "Net-(D39-Pad2)" "Net-(D40-Pad2)" "Net-(D41-Pad2)" ROW4 "Net-(D42-Pad2)" "Net-(D43-Pad2)" "Net-(D44-Pad2)"
+    "Net-(D45-Pad2)" "Net-(D46-Pad2)" "Net-(D47-Pad2)" "Net-(D48-Pad2)" "Net-(D49-Pad2)" "Net-(D50-Pad2)" "Net-(D51-Pad2)" "Net-(D52-Pad2)"
+    "Net-(D53-Pad2)" "Net-(D54-Pad2)" "Net-(D55-Pad2)" ROW5 "Net-(D56-Pad2)" "Net-(D57-Pad2)" "Net-(D58-Pad2)" "Net-(D59-Pad2)"
+    "Net-(D60-Pad2)" "Net-(D61-Pad2)" "Net-(D62-Pad2)" "Net-(D63-Pad2)" "Net-(D64-Pad2)" "Net-(D65-Pad2)" "Net-(D66-Pad2)" ROW6
+    "Net-(D67-Pad2)" "Net-(D68-Pad2)" "Net-(D69-Pad2)" "Net-(D70-Pad2)" "Net-(D71-Pad2)" "Net-(D72-Pad2)" "Net-(D73-Pad2)" "Net-(D74-Pad2)"
+    "Net-(D75-Pad2)" "Net-(D76-Pad2)" ROW7 "Net-(D77-Pad2)" "Net-(D78-Pad2)" "Net-(D79-Pad2)" "Net-(D80-Pad2)" "Net-(D81-Pad2)"
+    "Net-(D82-Pad2)" "Net-(D83-Pad2)" "Net-(D84-Pad2)" "Net-(D85-Pad2)" "Net-(D86-Pad2)" ROW8 "Net-(D87-Pad2)" "Net-(D88-Pad2)"
+    "Net-(D89-Pad2)" "Net-(D90-Pad2)" "Net-(D91-Pad2)" "Net-(D92-Pad2)" SCL0 SDA0 MISO0 MOSI0
+    COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8
+    COL9 COL10 COL11 COL12 COL13 COL14 /d2 /d3
+    rst /aref /e6 /e7 /e1 /pa1 /pa2 /pa3
+    /pa4 /pa5 /pa6 /pa7 /ale "Net-(D106-Pad3)" "Net-(D100-Pad1)" "Net-(D100-Pad3)"
+    "Net-(D101-Pad1)" "Net-(D102-Pad1)" "Net-(D102-Pad3)" "Net-(D103-Pad1)" "Net-(D104-Pad1)" "Net-(D104-Pad3)" "Net-(D105-Pad3)" "Net-(D105-Pad1)"
+    "Net-(D106-Pad1)" "Net-(D108-Pad1)" "Net-(D110-Pad1)" "Net-(D111-Pad3)" "Net-(D112-Pad1)" "Net-(D114-Pad1)" "Net-(D116-Pad1)" "Net-(D118-Pad1)"
+    "Net-(D120-Pad1)" "Net-(D122-Pad1)" "Net-(D124-Pad1)" "Net-(D126-Pad1)" "Net-(D130-Pad1)" "Net-(D132-Pad1)" "Net-(D135-Pad1)" "Net-(D137-Pad1)"
+    "Net-(D139-Pad1)" "Net-(D141-Pad1)" "Net-(D142-Pad1)" "Net-(D143-Pad1)" "Net-(D145-Pad1)" "Net-(D147-Pad1)" "Net-(D149-Pad1)" "Net-(D151-Pad1)"
+    "Net-(D153-Pad1)" "Net-(D155-Pad1)" "Net-(D157-Pad1)" "Net-(D159-Pad1)" "Net-(D162-Pad1)" "Net-(D164-Pad1)" "Net-(D166-Pad1)" "Net-(D168-Pad1)"
+    "Net-(D170-Pad1)" "Net-(D172-Pad1)" "Net-(D174-Pad1)" "Net-(D176-Pad1)" "Net-(D178-Pad1)" "Net-(D180-Pad1)" "Net-(D182-Pad1)" "Net-(D184-Pad1)"
+    "Net-(J1-Pad2)" "Net-(D93-Pad2)" "Net-(D94-Pad2)" "Net-(D95-Pad2)" "Net-(D96-Pad2)" "Net-(D97-Pad2)" "Net-(D98-Pad2)" /b0
+    /b1 /b4 /b5 ROW9 /d6 "Net-(D107-Pad3)" "Net-(D109-Pad3)" "Net-(D113-Pad3)"
+    "Net-(D115-Pad3)" "Net-(D117-Pad3)" "Net-(D119-Pad3)" "Net-(D121-Pad3)" "Net-(D123-Pad3)" "Net-(D125-Pad3)" "Net-(D127-Pad3)" "Net-(D128-Pad3)"
+    "Net-(D129-Pad3)" "Net-(D131-Pad3)" "Net-(D133-Pad3)" "Net-(D134-Pad3)" "Net-(D136-Pad3)" "Net-(D138-Pad3)" "Net-(D140-Pad3)" "Net-(D144-Pad3)"
+    "Net-(D146-Pad3)" "Net-(D148-Pad3)" "Net-(D150-Pad3)" "Net-(D152-Pad3)" "Net-(D154-Pad3)" "Net-(D156-Pad3)" "Net-(D158-Pad3)" "Net-(D160-Pad3)"
+    "Net-(D161-Pad3)" "Net-(D163-Pad3)" "Net-(D165-Pad3)" "Net-(D167-Pad3)" "Net-(D169-Pad3)" "Net-(D171-Pad3)" "Net-(D173-Pad3)" "Net-(D175-Pad3)"
+    "Net-(D177-Pad3)" "Net-(D179-Pad3)" "Net-(D181-Pad3)" "Net-(D183-Pad3)" "Net-(D185-Pad3)" "Net-(D186-Pad1)" "Net-(D188-Pad1)" "Net-(D191-Pad1)"
+    (clearance_class "kicad_default")
+    (via_rule kicad_default)
+    (rule
+      (width 250.0)
+    )
+    (circuit 
+      (use_layer F.Cu B.Cu)
+    )
+  )
+  (class GND
+    GND
+    (clearance_class GND)
+    (via_rule GND)
+    (rule
+      (width 500.0)
+    )
+    (circuit 
+      (use_layer F.Cu B.Cu)
+    )
+  )
+  (class VCC
+    +5V "LED_PWR"
+    (clearance_class VCC)
+    (via_rule VCC)
+    (rule
+      (width 500.0)
+    )
+    (circuit 
+      (use_layer F.Cu B.Cu)
+    )
+  )
+)
\ No newline at end of file
--- a/pcb_v4/dashie-keys.sch
+++ b/pcb_v4/dashie-keys.sch
--- a/pcb_v4/dashie-keys.ses
+++ b/pcb_v4/dashie-keys.ses
--- a/pcb_v4/dashie-keys.xml
+++ b/pcb_v4/dashie-keys.xml
--- a/pcb_v4/fp-info-cache
+++ b/pcb_v4/fp-info-cache
--- a/pcb_v4/fp-lib-table
+++ b/pcb_v4/fp-lib-table
+(fp_lib_table
+  (lib (name teensy)(type KiCad)(uri "$(KIPRJMOD)/../teensy.pretty")(options "")(descr ""))
+  (lib (name footprints_cherry)(type KiCad)(uri "$(KIPRJMOD)/../KiCAD-Keyboard-Tutorial/footprints.pretty")(options "")(descr ""))
+  (lib (name LoutreFilligrane)(type KiCad)(uri /home/dashie/datas/Seafile/dev/kicad/libs/dashie/LoutreFilligrane.pretty)(options "")(descr ""))
+  (lib (name Keebio-Parts)(type KiCad)(uri C:/Users/rhaam/Documents/GitHub/dashie-keys/Keebio-Parts.pretty)(options "")(descr ""))
+)
--- a/pcb_v4/sym-lib-table
+++ b/pcb_v4/sym-lib-table
+(sym_lib_table
+  (lib (name teensy)(type Legacy)(uri ${KIPRJMOD}/../teensy_library/teensy.lib)(options "")(descr ""))
+  (lib (name dashie-keys-rescue)(type Legacy)(uri ${KIPRJMOD}/dashie-keys-rescue.lib)(options "")(descr ""))
+)